As a circuit for controlling bit lines of a memory cell array, there is known a circuit including a plurality of data retention circuits for temporarily storing data supplied from a data input/output terminal, a plurality of buses connected respectively to the plurality of data retention circuits, and a plurality of data latch circuits connected commonly to one bus.
The data temporarily stored in the data retention circuit is transferred to the data latch circuits via the bus. The potential of the bit line is controlled in response to the data of the data latch circuit.